Multi-Level Cache Resizing

Hardware designers are constantly looking for ways to squeeze waste out of architectures to achieve better power efficiency. Cache resizing is a technique that can remove wasteful power consumption in caches. The idea is to determine the minimum cache a program needs to run at near-peak performance, and then reconfigure the cache to implement this efficient capacity. While there has been significant previous work on cache resizing, existing techniques have focused on controlling resizing for a single level of cache only. This sacrifices significant opportunities for power savings in modern CPU hierarchies which routinely employ 3 levels of cache. This paper investigates multi-level cache resizing (MCR). MCR independently resizes all caches in a modern cache hierarchy to minimize dynamic and static power consumption at all caching levels simultaneously. Specifically, we study a static-optimal version of MCR, and find resizing a 3-level hierarchy can reduce total energy dissipation by 58.9% with only 4.4% degradation in performance. Our study shows a non-trivial portion of this gain– 1 3rd for programs exhibiting good temporal locality–comes from optimizing the interactions between resizing decisions at different caching levels. We also propose several dynamic resizing algorithms that can automatically find good size configurations at runtime. Our results show dynamic MCR can achieve between 40–62% energy savings with slightly higher performance degradation than static-optimal MCR.